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Author	SHA1	Message	Date
Yi-Ting Shih	3c03c9d383	Fix: uart_hex wrong offset hw3 hw4	2025-04-15 17:44:28 +08:00
Yi-Ting Shih	c4a44542ef	Fix: interrupt preemption	2025-04-15 17:22:45 +08:00
Yi-Ting Shih	89ff8a018d	Fix: page state	2025-04-15 15:12:07 +08:00
Yi-Ting Shih	f25758031a	Fix: mman behavior	2025-04-15 14:20:52 +08:00
Yi-Ting Shih	d3d316a994	Add: README.md	2025-04-08 07:02:54 +08:00
Yi-Ting Shih	93bbddf364	Fix: lab3 on-board problems	2025-04-08 07:01:56 +08:00
Yi-Ting Shih	2d572cea4d	Fix: lab3 bug	2025-04-08 07:01:56 +08:00
Yi-Ting Shih	fc91808c1b	Fix: enable interrupt later	2025-04-08 07:01:56 +08:00
Yi-Ting Shih	b7da380421	Feat: lab 3	2025-04-08 07:01:24 +08:00
Yi-Ting Shih	e2ebb6cc34	Feat: lab 3 w/o adv 2	2025-04-08 07:01:24 +08:00
Yi-Ting Shih	98327b148a	Draft: lab 3 irq wtf	2025-04-08 07:01:24 +08:00
Yi-Ting Shih	9d19b8b3b6	Draft: start lab 3	2025-04-08 06:59:50 +08:00
Yi-Ting Shih	45ebb20cf2	Feat: lab 4	2025-04-08 06:59:50 +08:00
Yi-Ting Shih	ed2ced5caf	Feat: add memalloc command	2025-04-08 06:59:50 +08:00
Yi-Ting Shih	c0e474fa32	Fix: on board hw2	2025-04-08 06:59:50 +08:00
Yi-Ting Shih	be5045fde1	hw2 done	2025-04-08 06:59:49 +08:00
Yi-Ting Shih	41d4a30610	Fix: mbox output hw1	2025-04-08 06:59:49 +08:00
Yi-Ting Shih	010f9019e8	Fix: add gitignore	2025-04-08 06:59:49 +08:00
Yi-Ting Shih	e906741ee9	initial commit	2025-04-08 06:59:49 +08:00