Draft: start lab 3

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ytshih committed 2025-04-08 06:59:50 +08:00
1 parent 45ebb20cf2
commit 9d19b8b3b6
5 files changed
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@@ -36,3 +36,15 @@ void exit(int);
(ptr = (orig_type*)((bump_type*)ptr + 1)), \
((bump_type*)ptr - 1) \
)
#define R_SYSREG(ret, reg) \
asm volatile( \
"mrs %[a], " #reg \
: [a] "=r" (ret) \
)
#define W_SYSREG(val, reg) \
asm volatile( \
"msr " #reg ", %[a]" \
: [a] "r" (val) \
)