Ytshih/hw2
This commit is contained in:
Yi-Ting Shih
@@ -85,38 +85,38 @@ ShortToMachine(unsigned short shortword) { return ShortToHost(shortword); }
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bool
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Machine::ReadMem(int addr, int size, int *value)
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{
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int data;
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ExceptionType exception;
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int physicalAddress;
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DEBUG(dbgAddr, "Reading VA " << addr << ", size " << size);
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exception = Translate(addr, &physicalAddress, size, FALSE);
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if (exception != NoException) {
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RaiseException(exception, addr);
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return FALSE;
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}
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switch (size) {
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case 1:
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data = mainMemory[physicalAddress];
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*value = data;
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break;
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case 2:
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data = *(unsigned short *) &mainMemory[physicalAddress];
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*value = ShortToHost(data);
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break;
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case 4:
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data = *(unsigned int *) &mainMemory[physicalAddress];
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*value = WordToHost(data);
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break;
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int data;
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ExceptionType exception;
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int physicalAddress;
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default: ASSERT(FALSE);
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}
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DEBUG(dbgAddr, "\tvalue read = " << *value);
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return (TRUE);
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DEBUG(dbgAddr, "Reading VA " << addr << ", size " << size);
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exception = Translate(addr, &physicalAddress, size, FALSE);
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if (exception != NoException) {
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RaiseException(exception, addr);
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return FALSE;
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}
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switch (size) {
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case 1:
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data = mainMemory[physicalAddress];
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*value = data;
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break;
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case 2:
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data = *(unsigned short *) &mainMemory[physicalAddress];
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*value = ShortToHost(data);
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break;
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case 4:
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data = *(unsigned int *) &mainMemory[physicalAddress];
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*value = WordToHost(data);
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break;
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default: ASSERT(FALSE);
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}
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DEBUG(dbgAddr, "\tvalue read = " << *value);
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return (TRUE);
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}
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//----------------------------------------------------------------------
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@@ -135,35 +135,35 @@ Machine::ReadMem(int addr, int size, int *value)
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bool
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Machine::WriteMem(int addr, int size, int value)
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{
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ExceptionType exception;
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int physicalAddress;
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DEBUG(dbgAddr, "Writing VA " << addr << ", size " << size << ", value " << value);
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ExceptionType exception;
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int physicalAddress;
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exception = Translate(addr, &physicalAddress, size, TRUE);
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if (exception != NoException) {
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RaiseException(exception, addr);
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return FALSE;
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}
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switch (size) {
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case 1:
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mainMemory[physicalAddress] = (unsigned char) (value & 0xff);
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break;
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DEBUG(dbgAddr, "Writing VA " << addr << ", size " << size << ", value " << value);
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case 2:
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*(unsigned short *) &mainMemory[physicalAddress]
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= ShortToMachine((unsigned short) (value & 0xffff));
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break;
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case 4:
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*(unsigned int *) &mainMemory[physicalAddress]
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= WordToMachine((unsigned int) value);
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break;
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default: ASSERT(FALSE);
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}
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return TRUE;
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exception = Translate(addr, &physicalAddress, size, TRUE);
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if (exception != NoException) {
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RaiseException(exception, addr);
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return FALSE;
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}
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switch (size) {
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case 1:
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mainMemory[physicalAddress] = (unsigned char) (value & 0xff);
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break;
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case 2:
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*(unsigned short *) &mainMemory[physicalAddress]
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= ShortToMachine((unsigned short) (value & 0xffff));
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break;
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case 4:
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*(unsigned int *) &mainMemory[physicalAddress]
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= WordToMachine((unsigned int) value);
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break;
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default: ASSERT(FALSE);
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}
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return TRUE;
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}
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//----------------------------------------------------------------------
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@@ -184,67 +184,75 @@ Machine::WriteMem(int addr, int size, int value)
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ExceptionType
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Machine::Translate(int virtAddr, int* physAddr, int size, bool writing)
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{
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int i;
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unsigned int vpn, offset;
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TranslationEntry *entry;
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unsigned int pageFrame;
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int i;
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unsigned int vpn, offset;
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TranslationEntry *entry;
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unsigned int pageFrame;
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DEBUG(dbgAddr, "\tTranslate " << virtAddr << (writing ? " , write" : " , read"));
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DEBUG(dbgAddr, "\tTranslate " << virtAddr << (writing ? " , write" : " , read"));
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// check for alignment errors
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if (((size == 4) && (virtAddr & 0x3)) || ((size == 2) && (virtAddr & 0x1))){
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DEBUG(dbgAddr, "Alignment problem at " << virtAddr << ", size " << size);
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return AddressErrorException;
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// check for alignment errors
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if (((size == 4) && (virtAddr & 0x3)) || ((size == 2) && (virtAddr & 0x1))){
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DEBUG(dbgAddr, "Alignment problem at " << virtAddr << ", size " << size);
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return AddressErrorException;
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}
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// we must have either a TLB or a page table, but not both!
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ASSERT(tlb == NULL || pageTable == NULL);
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ASSERT(tlb != NULL || pageTable != NULL);
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// calculate the virtual page number, and offset within the page,
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// from the virtual address
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vpn = (unsigned) virtAddr / PageSize;
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offset = (unsigned) virtAddr % PageSize;
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if (tlb == NULL) { // => page table => vpn is index into table
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if (vpn >= pageTableSize) {
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DEBUG(dbgAddr, "Illegal virtual page # " << virtAddr);
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DEBUG(dbgAddr, "vpn, pageTableSize, NumPhysPages: " << vpn << ' ' << pageTableSize << ' ' << NumPhysPages);
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return AddressErrorException;
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} else if (!pageTable[vpn].valid) {
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DEBUG(dbgAddr, "Invalid virtual page # " << virtAddr);
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return PageFaultException;
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}
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// we must have either a TLB or a page table, but not both!
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ASSERT(tlb == NULL || pageTable == NULL);
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ASSERT(tlb != NULL || pageTable != NULL);
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// calculate the virtual page number, and offset within the page,
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// from the virtual address
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vpn = (unsigned) virtAddr / PageSize;
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offset = (unsigned) virtAddr % PageSize;
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if (tlb == NULL) { // => page table => vpn is index into table
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if (vpn >= pageTableSize) {
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DEBUG(dbgAddr, "Illegal virtual page # " << virtAddr);
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return AddressErrorException;
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} else if (!pageTable[vpn].valid) {
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DEBUG(dbgAddr, "Invalid virtual page # " << virtAddr);
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return PageFaultException;
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}
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entry = &pageTable[vpn];
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} else {
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for (entry = NULL, i = 0; i < TLBSize; i++)
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if (tlb[i].valid && (tlb[i].virtualPage == ((int)vpn))) {
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entry = &tlb[i]; // FOUND!
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break;
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}
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if (entry == NULL) { // not found
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DEBUG(dbgAddr, "Invalid TLB entry for this virtual page!");
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return PageFaultException; // really, this is a TLB fault,
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// the page may be in memory,
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// but not in the TLB
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}
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entry = &pageTable[vpn];
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} else {
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for (entry = NULL, i = 0; i < TLBSize; i++)
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if (tlb[i].valid && (tlb[i].virtualPage == ((int)vpn))) {
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entry = &tlb[i]; // FOUND!
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break;
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}
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if (entry == NULL) { // not found
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DEBUG(dbgAddr, "Invalid TLB entry for this virtual page!");
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return PageFaultException; // really, this is a TLB fault,
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// the page may be in memory,
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// but not in the TLB
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}
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}
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if (entry->readOnly && writing) { // trying to write to a read-only page
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DEBUG(dbgAddr, "Write to read-only page at " << virtAddr);
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return ReadOnlyException;
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if (entry->readOnly && writing) { // trying to write to a read-only page
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DEBUG(dbgAddr, "Write to read-only page at " << virtAddr);
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return ReadOnlyException;
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}
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pageFrame = entry->physicalPage;
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if (pageFrame == -1) {
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pageFrame = entry->physicalPage = kernel->frameTable->Allocate();
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if (pageFrame == -1) {
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DEBUG(dbgAddr, "Memory Limit exceeded");
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return MemoryLimitException;
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}
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pageFrame = entry->physicalPage;
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}
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// if the pageFrame is too big, there is something really wrong!
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// An invalid translation was loaded into the page table or TLB.
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if (pageFrame >= NumPhysPages) {
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DEBUG(dbgAddr, "Illegal pageframe " << pageFrame);
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return BusErrorException;
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}
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entry->use = TRUE; // set the use, dirty bits
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if (writing)
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entry->dirty = TRUE;
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*physAddr = pageFrame * PageSize + offset;
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ASSERT((*physAddr >= 0) && ((*physAddr + size) <= MemorySize));
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DEBUG(dbgAddr, "phys addr = " << *physAddr);
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return NoException;
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// if the pageFrame is too big, there is something really wrong!
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// An invalid translation was loaded into the page table or TLB.
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if (pageFrame >= NumPhysPages) {
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DEBUG(dbgAddr, "Illegal pageframe " << pageFrame);
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return BusErrorException;
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}
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entry->use = TRUE; // set the use, dirty bits
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if (writing)
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entry->dirty = TRUE;
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*physAddr = pageFrame * PageSize + offset;
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ASSERT((*physAddr >= 0) && ((*physAddr + size) <= MemorySize));
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DEBUG(dbgAddr, "phys addr = " << *physAddr);
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return NoException;
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}
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