Ytshih/hw2
This commit is contained in:
Yi-Ting Shih
@@ -28,32 +28,34 @@
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// Definitions related to the size, and format of user memory
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const int PageSize = 128; // set the page size equal to
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// the disk sector size, for simplicity
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// the disk sector size, for simplicity
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//
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// You are allowed to change this value.
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// Doing so will change the number of pages of physical memory
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// available on the simulated machine.
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//
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//
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// You are allowed to change this value.
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// Doing so will change the number of pages of physical memory
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// available on the simulated machine.
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//
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const int NumPhysPages = 128;
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const int MemorySize = (NumPhysPages * PageSize);
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const int TLBSize = 4; // if there is a TLB, make it small
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enum ExceptionType { NoException, // Everything ok!
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SyscallException, // A program executed a system call.
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PageFaultException, // No valid translation found
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ReadOnlyException, // Write attempted to page marked
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// "read-only"
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BusErrorException, // Translation resulted in an
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// invalid physical address
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AddressErrorException, // Unaligned reference or one that
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// was beyond the end of the
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// address space
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OverflowException, // Integer overflow in add or sub.
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IllegalInstrException, // Unimplemented or reserved instr.
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NumExceptionTypes
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enum ExceptionType {
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NoException, // Everything ok!
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SyscallException, // A program executed a system call.
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PageFaultException, // No valid translation found
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ReadOnlyException, // Write attempted to page marked
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// "read-only"
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BusErrorException, // Translation resulted in an
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// invalid physical address
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AddressErrorException, // Unaligned reference or one that
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// was beyond the end of the
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// address space
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OverflowException, // Integer overflow in add or sub.
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IllegalInstrException, // Unimplemented or reserved instr.
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MemoryLimitException, // Bad allocation
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NumExceptionTypes
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};
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// User program CPU state. The full set of MIPS registers, plus a few
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@@ -94,97 +96,97 @@ class Interrupt;
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class Machine {
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public:
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Machine(bool debug); // Initialize the simulation of the hardware
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// for running user programs
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// for running user programs
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~Machine(); // De-allocate the data structures
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// Routines callable by the Nachos kernel
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// Routines callable by the Nachos kernel
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void Run(); // Run a user program
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int ReadRegister(int num); // read the contents of a CPU register
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void WriteRegister(int num, int value);
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// store a value into a CPU register
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// store a value into a CPU register
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// Data structures accessible to the Nachos kernel -- main memory and the
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// page table/TLB.
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//
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// Note that *all* communication between the user program and the kernel
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// are in terms of these data structures (plus the CPU registers).
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// Data structures accessible to the Nachos kernel -- main memory and the
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// page table/TLB.
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//
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// Note that *all* communication between the user program and the kernel
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// are in terms of these data structures (plus the CPU registers).
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char *mainMemory; // physical memory to store user program,
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// code and data, while executing
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// code and data, while executing
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// NOTE: the hardware translation of virtual addresses in the user program
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// to physical addresses (relative to the beginning of "mainMemory")
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// can be controlled by one of:
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// a traditional linear page table
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// a software-loaded translation lookaside buffer (tlb) -- a cache of
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// mappings of virtual page #'s to physical page #'s
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//
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// If "tlb" is NULL, the linear page table is used
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// If "tlb" is non-NULL, the Nachos kernel is responsible for managing
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// the contents of the TLB. But the kernel can use any data structure
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// it wants (eg, segmented paging) for handling TLB cache misses.
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//
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// For simplicity, both the page table pointer and the TLB pointer are
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// public. However, while there can be multiple page tables (one per address
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// space, stored in memory), there is only one TLB (implemented in hardware).
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// Thus the TLB pointer should be considered as *read-only*, although
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// the contents of the TLB are free to be modified by the kernel software.
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// NOTE: the hardware translation of virtual addresses in the user program
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// to physical addresses (relative to the beginning of "mainMemory")
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// can be controlled by one of:
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// a traditional linear page table
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// a software-loaded translation lookaside buffer (tlb) -- a cache of
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// mappings of virtual page #'s to physical page #'s
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//
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// If "tlb" is NULL, the linear page table is used
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// If "tlb" is non-NULL, the Nachos kernel is responsible for managing
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// the contents of the TLB. But the kernel can use any data structure
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// it wants (eg, segmented paging) for handling TLB cache misses.
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//
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// For simplicity, both the page table pointer and the TLB pointer are
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// public. However, while there can be multiple page tables (one per address
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// space, stored in memory), there is only one TLB (implemented in hardware).
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// Thus the TLB pointer should be considered as *read-only*, although
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// the contents of the TLB are free to be modified by the kernel software.
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TranslationEntry *tlb; // this pointer should be considered
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// "read-only" to Nachos kernel code
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// "read-only" to Nachos kernel code
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TranslationEntry *pageTable;
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unsigned int pageTableSize;
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bool ReadMem(int addr, int size, int* value);
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bool WriteMem(int addr, int size, int value);
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// Read or write 1, 2, or 4 bytes of virtual
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// memory (at addr). Return FALSE if a
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// correct translation couldn't be found.
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// Read or write 1, 2, or 4 bytes of virtual
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// memory (at addr). Return FALSE if a
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// correct translation couldn't be found.
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private:
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// Routines internal to the machine simulation -- DO NOT call these directly
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// Routines internal to the machine simulation -- DO NOT call these directly
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void DelayedLoad(int nextReg, int nextVal);
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// Do a pending delayed load (modifying a reg)
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// Do a pending delayed load (modifying a reg)
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void OneInstruction(Instruction *instr);
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// Run one instruction of a user program.
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// Run one instruction of a user program.
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ExceptionType Translate(int virtAddr, int* physAddr, int size,bool writing);
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// Translate an address, and check for
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// alignment. Set the use and dirty bits in
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// the translation entry appropriately,
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// and return an exception code if the
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// translation couldn't be completed.
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// Translate an address, and check for
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// alignment. Set the use and dirty bits in
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// the translation entry appropriately,
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// and return an exception code if the
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// translation couldn't be completed.
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void RaiseException(ExceptionType which, int badVAddr);
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// Trap to the Nachos kernel, because of a
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// system call or other exception.
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// Trap to the Nachos kernel, because of a
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// system call or other exception.
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void Debugger(); // invoke the user program debugger
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void DumpState(); // print the user CPU and memory state
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// Internal data structures
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// Internal data structures
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int registers[NumTotalRegs]; // CPU registers, for executing user programs
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bool singleStep; // drop back into the debugger after each
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// simulated instruction
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// simulated instruction
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int runUntilTime; // drop back into the debugger when simulated
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// time reaches this value
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// time reaches this value
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friend class Interrupt; // calls DelayedLoad()
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};
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extern void ExceptionHandler(ExceptionType which);
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// Entry point into Nachos for handling
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// user system calls and exceptions
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// Defined in exception.cc
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// Entry point into Nachos for handling
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// user system calls and exceptions
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// Defined in exception.cc
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// Routines for converting Words and Short Words to and from the
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